As faster operation of computers has been sought, numerous hardware/firmware features have been employed to achieve that purpose. One widely incorporated feature directed to increasing the speed of operation is pipelining in which the various stages of execution of a series of consecutive machine level instructions are undertaken simultaneously. Thus, in a simple example, during a given time increment, a first stage of a fourth (in order of execution) instruction may be carried out while a second stage of a third instruction, a third stage of a second instruction and a fourth stage of a first instruction are all performed simultaneously.
Pipelining dramatically increases the apparent speed of operation of a computer system. However, there are instances in which conflicts or problems arise among the sequential instructions which can cause pipeline breaks or even processor errors which can adversely affect processor performance since the affected instructions must often be retried.
One specific problem which has arisen in the use of pipelined processors relates to an instruction stream in which a conditional transfer (or conditional branch) follows immediately after an instruction the execution of which can affect the condition which might direct the conditional transfer. That is, in a simple example, an instruction to add a specified operand to the present contents of the accumulator register might be followed by a conditional transfer instruction which calls for a transfer of instruction flow if the result of the previous instruction is zero. Since the result is not known until late in the execution sequence of the first instruction, a zero indicator flag cannot be set until that time. Accordingly, the succeeding conditional transfer instruction is itself into the late stages of its execution such that it must test the flag virtually immediately. In many pipelined processors, an indicator flag is both set (if appropriate) and tested in the same clock cycle.
In the past, this fact did not establish an intolerable logic race; a flag could be set early in a clock cycle and accurately tested late in the same clock cycle. However, as the physical size of integrated circuits has been remarkably reduced and the degree of integration accordingly increased, it has been possible to greatly improve the performance of a given processor configuration by merely increasing the clock speed in the more highly integrated versions. On the other hand, it has been found that there is limit to the extent to which the clock rate can be increased before the indicator flag test carried out by a conditional transfer instruction becomes unreliable. Thus, if the clock rate for a given process or configuration is sufficiently increased, numerous faults and retries may be generated and required to the detriment of overall system performance; in effect, an error prone logic race condition has been created.
Yet, it will be apparent to those skilled in the art that there is great value in building on a proven processor configuration and that it consequently would be highly desirable to provide, in a simple, reliable and economic manner, for increasing the clock rate of a pipelined processor configuration without causing a logic race condition associated with the use of conditional transfer instructions.